1. Field of the Invention
The present invention relates to a level conversion technology, and it particularly relates to level conversion circuits which convert the voltage amplitude of an input signal to another voltage amplitude.
2. Description of the Related Art
Chips which are called “system on silicon” have been developed as integrated circuits utilizing bulk silicon in recent years, which have microprocessors or memories together with logic circuits on a same chip. Technologies to fabricate the chips are accordingly being developed nowadays, which enable to manufacture a chip that has various circuits with as fine design rules as possible.
The circuits are, however, designed according to respectively different design rules. It is, therefore, unavoidable to integrate the circuits which have the different design rules on a same chip. As a result, a chip comes to have the circuits which operate with different supply voltages and it is required to convert the level of voltage at the interface of each circuit. Moreover, level conversion circuits are naturally required to operate at high speed because pursuing high-speed operation is one original object of providing various circuits on one chip.
Thin film transistors which are made of polycrystalline silicon are generally utilized for display devices such as liquid crystal display, organic EL (Electro Luminescence) and so forth. Level conversion circuits are normally structured by thin film transistors made of polycrystalline silicon in providing the level conversion circuits and these display devices on a same substrate. The characteristics of elements often shift from designed values in manufacturing transistors, such as threshold voltage or the like. Providing level conversion circuits which can accurately operate is required though the characteristics of elements widely shift from the designed values particularly in fabricating thin film transistors made of polycrystalline silicon. Level conversion circuits which can operate even when input signals with small amplitude are given are also required for these display devices, from the view point of power saving and pursuing high-definition.
FIG. 1 is a circuit diagram showing the first example of a known level conversion circuit. A level conversion circuit 800 comprises two p-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 801, 802 and two n-channel MOSFETs 803, 804. The p-channel MOSFET 801 is connected between a supply terminal which receives supply voltage VDD and an output node N11 and the p-channel MOSFET 802 is connected between the supply terminal and an output node N12. The n-channel MOSFET 803 is connected between the output node N11 and a ground lug and the n-channel MOSFET 804 is connected between the output node N12 and the ground lug. The gates of the p-channel MOSFETs 801 and 802 are respectively connected to the nodes N12 and N11 in a crossing manner. Input signals CLK1 and CLK2 are respectively inputted to the gates of the n-channel MOSFETs 803 and 804, which change complementarily.
The n-channel MOSFET 803 is ON and the n-channel MOSFET 804 is OFF when the input signal CLK1 becomes high and the input signal CLK2 becomes low. Accordingly, the p-channel MOSFET 802 becomes ON and the p-channel MOSFET 801 becomes OFF. As a result, the output voltage Vout of the output node N12 is increased. On the contrary, the output voltage Vout of the output node N12 is decreased when the input signal CLK1 becomes low and the input signal CLK2 becomes high.
It is necessary for the n-channel MOSFETs 803 and 804 to be ON that the voltage amplitude of the input signals CLK1 and CLK2 is larger than the threshold voltage Vtn of the n-channel MOSFETs 803 and 804. The level conversion circuit 800 is, therefore, utilized when the input signals and output signals are in small voltage ratio. The circuit 800 is, for example, suitable for being utilized in converting the signals of 3V system to the signals of 5V system, converting the signals of 2.5V system to the signals of 3V system or converting the signals of 1.8V system to the signals of 2.5V or 3.3V system.
FIG. 2 is a circuit diagram showing the second example of a known level conversion circuit. A level conversion circuit 810 comprises a bias circuit 811, a p-channel MOSFET 812 and a n-channel MOSFET 813.
The p-channel MOSFET 812 is connected between a supply terminal which receives supply voltage VDD and an output node N13. The n-channel MOSFET 813 is connected between the output node N13 and a supply terminal which receives prescribed voltage VEE. An input signal CLK is inputted to the gate of the n-channel MOSFET 812 and the bias circuit 811. The bias circuit 811 inputs the input signal to the gate of the n-channel MOSFET 813 after shifting the center level of the input signal.
The p-channel MOSFET 812 is OFF and the n-channel MOSFET 813 is ON when the input signal CLK becomes high. As a result, the output voltage Vout of the output node N13 is decreased. The p-channel MOSFET 812 is ON and the n-channel MOSFET 813 is OFF when the input signal CLK becomes low. As a result, the output voltage Vout of the output node N13 is increased.
This circuit can be set to operate even when the voltage amplitude of the input signal CLK is smaller than the threshold voltage of the n-channel MOSFET 813 because the bias circuit 811 shifts the center level of the input signal CLK.
FIG. 3 is a circuit diagram showing the third example of a known level conversion circuit. A level conversion circuit 820 comprises a clamp circuit 821 and an amplifying circuit 822 of a current mirror type. The amplifying circuit 822 of the current mirror type comprises two p-channel MOSFETs 831, 832 and two n-channel MOSFETs 833, 834. The p-channel MOSFET 831 is connected between a supply terminal which receives supply voltage VDD and an output node N14 and the p-channel MOSFET 832 is connected between the supply terminal and an output node N15. The n-channel MOSFET 833 is connected between the output node N14 and a ground lug and the n-channel MOSFET 834 is connected between the output node N15 and the ground lug. The gates of the p-channel MOSFETs 831 and 832 are connected to the output node N14. The clamp circuit 821 inputs input signals CLK1 and CLK2, which change complementarily, to the gates of the n-channel MOSFETs 833 and 834 after shifting the center level of the input signals.
The n-channel MOSFET 833 is ON and the n-channel MOSFET 834 is OFF when the input signal CLK1 becomes high and the input signal CLK2 becomes low. Accordingly, the p-channel MOSFETs 831 and 832 become ON. As a result, the output voltage Vout of the output node N15 is increased. On the contrary, the output voltage Vout of the output node N15 is decreased when the input signal CLK1 becomes low and the input signal CLK2 becomes high.
This circuit can operate even when the voltage amplitude of the input signals CLK1 and CLK2 is smaller than the threshold voltage Vtn of the n-channel MOSFETs 833 and 834 because the clamp circuit 821 shifts the center level of the input signals CLK1 and CLK2.
FIG. 4 is a circuit diagram showing the fourth example of a known level conversion circuit. A level conversion circuit 840 shown in the FIG. 4 comprises a clamp circuit 841 and an amplifying circuit 842 of a PMOS cross couple type.
The amplifying circuit 842 of the PMOS cross couple type comprises two p-channel MOSFETs 851, 852 and two n-channel MOSFETs 853, 854. The p-channel MOSFET 851 is connected between a supply terminal which receives supply voltage VDD and an output node N16 and the p-channel MOSFET 852 is connected between the supply terminal and an output node N17. The n-channel MOSFET 853 is connected between the output node N16 and a ground lug and the n-channel MOSFET 854 is connected between the output node N17 and the ground lug. The gates of the p-channel MOSFETs 851 and 852 are respectively connected to the nodes N17 and N16 in a crossing manner. The clamp circuit 841 inputs input signals CLK1 and CLK2, which change complementarily, to the gates of the n-channel MOSFETs 853 and 854 after shifting the center level of the input signals.
The n-channel MOSFET 853 is ON and the n-channel MOSFET 854 is OFF when the input signal CLK1 becomes high and the input signal CLK2 becomes low. Accordingly, the p-channel MOSFET 851 becomes OFF and the p-channel MOSFET 852 becomes ON. As a result, the output voltage Vout of the output node N17 is increased. On the contrary, the output voltage Vout of the output node N17 is decreased when the input signal CLK1 becomes low and the input signal CLK2 becomes high.
This circuit can operate even when the voltage amplitude of the input signals CLK1 and CLK2 is smaller than the threshold voltage Vtn of the n-channel MOSFETs 853 and 854 because the clamp circuit 841 shifts the center level of the input signals CLK1 and CLK2.
The level conversion circuit shown in FIG. 1 can not operate when the voltage amplitude of the input signals CLK1 and CLK2 is smaller than the threshold voltage Vtn of the n-channel MOSFETs 803 and 804.
The level conversion circuit 810 shown in FIG. 2 can operate even when the voltage amplitude of the input signal CLK is smaller than the threshold voltage Vtn of the n-channel MOSFET 813 due to the existence of the bias circuit 811. The level conversion circuits 820 and 840 shown in FIG. 3 and FIG. 4 similarly can operate when the voltage amplitude of the input signals CLK1 and CLK2 is smaller than the threshold voltage Vtn of the n-channel MOSFET 833, 834, 853 and 854 due to the existence of the clamp circuits 821 and 841.
The level conversion circuits 810, 820 and 840, however, can not operate in the case the threshold voltage Vtn of the n-channel MOSFETs shifts widely from a designed value due to irregularity caused in manufacturing process.
The duty ratios of the output voltage waveforms of the level conversion circuits 800, 810, 820 and 840 shown in FIGS. 1, 2, 3 and 4 shift from predetermined designed values in the case that threshold voltages of the p-channel MOSFETs and the n-channel MOSFETs irregularly shift from designed values while being manufactured, such as the case which the threshold voltage Vtp of the p-channel MOSFETs is higher and the threshold voltage Vtn of the n-channel MOSFETs is lower than the designed values, or the case which the threshold voltage Vtp of the p-channel MOSFETs is lower and the threshold voltage Vtn of the n-channel MOSFETs is higher than the designed values. Each duration of on and off status of pixels shifts from designed values in a plurality of display devices if the duty ratios of signals do not remain 50%, especially in utilizing the level conversion circuits for acquiring the clock signals of the display devices.
The electric charge of the gates of the p-channel MOSFETs 801 and 802 are respectively transferred from one to the other when the ON and OFF status of the n-channel MOSFETs 803 and 804 is inverted in the level conversion circuit 800 shown in FIG. 1. The operation at high speed, therefore, can not be realized because time for inverting the level of the output voltage Vout is required. The time required becomes longer if transistors which do not have high operation capacity are utilized as the p-channel MOSFETs 801 and 802, such as thin film transistors made of polycrystalline silicon. Electric power consumed increases according to the length of the time required for inverting the level of the output voltage Vout because there flows penetration current to the ground lug, which flows from supply terminal to the ground lug through the route of p-channel MOSFET 801 and n-channel MOSFET 803 or the route of p-channel MOSFET 802 and n-channel MOSFET 804.
There is also room of improvement for the level conversion circuits 820 and 840 shown in FIG. 3 and 4 because the clamp circuits 821 and 824 provided thereto generally occupy large areas.